On Wed, Sep 07, 2016 at 11:22:14PM +0300, Sergei Shtylyov wrote: > From: Grigory Kletsko <grigory.kletsko@xxxxxxxxxxxxxxxxxx> > > Initially, the PCIe link speed is set up only at 2.5 GT/s. > For better performance, we're trying to increase link speed to 5 GT/s. > > [Sergei Shtylyov: indented the macro definitions with tabs, renamed the > SPCHG register bits for consistency, renamed the link speed field/values, > fixed too long lines, fixed redundancy in clearing the MACSR register bits, > fixed grammar/typos in the comments/messages, removed unrelated/useless > changes, fixed bugs in rcar_rwm32() calls done to set the bits, removed > unneeded braces, removed non-informative comment, reworded the patch > summary/description.] > > Signed-off-by: Grigory Kletsko <grigory.kletsko@xxxxxxxxxxxxxxxxxx> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx> Acked-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
