Instead of hard coding the product register in the rcar-du, use
the framework for it to get the SoC version and the revision needed
for the enabling the workaround.
Signed-off-by: Dirk Behme <dirk.behme@xxxxxxxxxxxx>
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index e10943b..ee639a6 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -13,6 +13,7 @@
#include <linux/clk.h>
#include <linux/mutex.h>
+#include <linux/soc/renesas/rcar3-prr.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
@@ -30,12 +31,6 @@
#include "rcar_du_regs.h"
#include "rcar_du_vsp.h"
-#define PRODUCT_REG 0xfff00044
-#define PRODUCT_H3_BIT (0x4f << 8)
-#define PRODUCT_MASK (0x7f << 8)
-#define CUT_ES1 (0x00)
-#define CUT_ES1_MASK (0x000000ff)
-
static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
{
struct rcar_du_device *rcdu = rcrtc->group->dev;
@@ -167,7 +162,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
u32 div;
u32 dpll_reg = 0;
struct dpll_info *dpll;
- void __iomem *product_reg;
bool h3_es1_workaround = false;
dpll = kzalloc(sizeof(*dpll), GFP_KERNEL);
@@ -175,11 +169,8 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
return;
/* DU2 DPLL Clock Select bit workaround in R-Car H3(ES1.0) */
- product_reg = ioremap(PRODUCT_REG, 0x04);
- if (((readl(product_reg) & PRODUCT_MASK) == PRODUCT_H3_BIT)
- && ((readl(product_reg) & CUT_ES1_MASK) == CUT_ES1))
+ if (cpu_is_rcar3_h3() && revision_is_rcar3_es1())
h3_es1_workaround = true;
- iounmap(product_reg);
/* Compute the clock divisor and select the internal or external dot
* clock based on the requested frequency.
--
2.8.0
