Hi Laurent > > > The parent clock isn't documented in the datasheet, use S2D1 as a best > > > guess for now. > > > > Would you be able to find out what the parent clock is for the FCP and LVDS > > (patch 2/9) clocks ? > > Thanks ! > I asked it to HW team It is too late information for you LVDS (APB) is using S0D4 (200MHz)
