From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
And put LAST_DT_CORE_CLK to a place where it won't be missed on updates.
Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
---
Since RFC, moved CLK_RINT to the end and reworked LAST_DT_CORE_CLK
drivers/clk/renesas/r8a7795-cpg-mssr.c | 8 ++++----
include/dt-bindings/clock/r8a7795-cpg-mssr.h | 2 ++
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index a9f933055663cb..d305bcd3ef6619 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -28,11 +28,8 @@
enum clk_ids {
- /* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
-
/* External Input Clocks */
- CLK_EXTAL,
+ CLK_EXTAL = LAST_DT_CORE_CLK + 1,
CLK_EXTALR,
/* Internal Core Clocks */
@@ -116,6 +113,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+
+ DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, 0x0240, 8),
+ DEF_DIV6_RO("r_int", R8A7795_CLK_RINT, CLK_EXTAL, 0x0240, 32),
};
static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
index e864aae0a2561c..274c2728e6dff5 100644
--- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
@@ -59,5 +59,7 @@
#define R8A7795_CLK_CPEX 44
#define R8A7795_CLK_R 45
#define R8A7795_CLK_OSC 46
+#define R8A7795_CLK_RINT 47
+#define LAST_DT_CORE_CLK R8A7795_CLK_RINT
#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
--
2.7.0
