So, since the new Gen3 manual has not only the RWDT but also the SWDT watchdog, here is a small series how I'd think we could enable the clocks for them. Only tested for the internal RCLK case, not for EXTALR yet. Release early, so we can talk about the approach... Please let me know if I am on the right track. Do we have a way to change a register which can only be changed in secure mode? I'd like to test the SWDT, but need to ungate its reset signal to the RST module. Thanks, Wolfram Wolfram Sang (5): clk: shmobile: r8a7795: make SD clk definition specific for GEN3 clk: shmobile: cpg-mssr: add generic support for read-only DIV6 clocks clk: shmobile: r8a7795: add OSC and R_INT clocks WIP: clk: shmobile: r8a7795: add R clk clk: shmobile: r8a7795: add stop for R clk drivers/clk/shmobile/r8a7795-cpg-mssr.c | 32 ++++++++++++++++++++++++---- drivers/clk/shmobile/renesas-cpg-mssr.c | 18 ++++++++++------ drivers/clk/shmobile/renesas-cpg-mssr.h | 6 +++--- include/dt-bindings/clock/r8a7795-cpg-mssr.h | 5 +++-- 4 files changed, 46 insertions(+), 15 deletions(-) -- 2.7.0
