Hi Geert, Thanks for the patch. > From: Geert Uytterhoeven [mailto:geert+renesas@xxxxxxxxx] > Sent: 18 February 2016 14:30 > > cpg_div6_clock_set_rate() only programs the new divisor if the clock isn't > stopped. If the clock is stopped, it will update the cached divisor value > only, which will be programmed into the clock registers when enabling the > clock later. > > However, cpg_div6_clock_recalc_rate() reads the divisor from the clock > registers instead of using the cached value, leading to an incorrect > result if the clock is currently stopped. > > Make cpg_div6_clock_recalc_rate() use the cached value to fix this. > > Reported-by: Ramesh Shanmugasundaram > <ramesh.shanmugasundaram@xxxxxxxxxxxxxx> > Suggested-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- > Ramesh: Can you please give this a try? Thanks! Tested-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@xxxxxxxxxxxxxx> > --- > drivers/clk/shmobile/clk-div6.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk- > div6.c index 9999947694509d58..0627860233cbf97e 100644 > --- a/drivers/clk/shmobile/clk-div6.c > +++ b/drivers/clk/shmobile/clk-div6.c > @@ -82,9 +82,8 @@ static unsigned long cpg_div6_clock_recalc_rate(struct > clk_hw *hw, > unsigned long parent_rate) > { > struct div6_clock *clock = to_div6_clock(hw); > -unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; > > -return parent_rate / div; > +return parent_rate / clock->div; > } > > static unsigned int cpg_div6_clock_calc_div(unsigned long rate, > -- > 1.9.1 Thanks, Ramesh Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
