On 3/12/24 7:13 AM, Krzysztof Kozlowski wrote: > On 11/03/2024 18:59, Tanmay Shah wrote: >> From: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> >> >> Introduce bindings for TCM memory address space on AMD-xilinx Zynq >> UltraScale+ platform. It will help in defining TCM in device-tree >> and make it's access platform agnostic and data-driven. >> >> Tightly-coupled memories(TCMs) are low-latency memory that provides >> predictable instruction execution and predictable data load/store >> timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory >> banks on the ATCM and BTCM ports, for a total of 128 KB of memory. >> >> The TCM resources(reg, reg-names and power-domain) are documented for >> each TCM in the R5 node. The reg and reg-names are made as required >> properties as we don't want to hardcode TCM addresses for future >> platforms and for zu+ legacy implementation will ensure that the >> old dts w/o reg/reg-names works and stable ABI is maintained. >> >> It also extends the examples for TCM split and lockstep modes. >> >> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> >> Signed-off-by: Tanmay Shah <tanmay.shah@xxxxxxx> >> --- >> >> Changes in v13: >> - Have power-domains property for lockstep case instead of >> keeping it flexible. >> - Add "items:" list in power-domains property > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Hi Krzysztof, Thanks for RB. I provided explanation of flexible power-domains in previous patchset. I am happy to send new revision removing minItems if you dis-agree. Thanks. > > Best regards, > Krzysztof >
