Previously, SCP core 0 controlled the power of L2TCM and dictated that
SCP core 1 could only boot after SCP core 0. To address this constraint,
extracted the power control flow of L2TCM and made it shared
between both cores, enabling support of arbitrary boot order.
The flow for controlling L2TCM power has been incorporated into the
mt8195_scp_before_load() and mt8195_scp_stop() APIs, which are
respectively invoked during the rproc->ops->start() and
rproc->ops->stop() operations. These APIs effectively serve the same
purpose as the rproc prepare()/unprepare() APIs."
Signed-off-by: Tinghan Shen <tinghan.shen@xxxxxxxxxxxx>
---
drivers/remoteproc/mtk_common.h | 1 +
drivers/remoteproc/mtk_scp.c | 80 ++++++++++++++++++++++++++-------
2 files changed, 66 insertions(+), 15 deletions(-)
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index 56395e8664cb..41e1b4732b75 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -130,6 +130,7 @@ struct mtk_scp {
struct rproc_subdev *rpmsg_subdev;
struct list_head elem;
+ struct platform_device *cluster_pdev;
};
/**
diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
index 3349488e5f21..94602272c05f 100644
--- a/drivers/remoteproc/mtk_scp.c
+++ b/drivers/remoteproc/mtk_scp.c
@@ -29,6 +29,10 @@ struct mtk_scp_of_cluster {
size_t l1tcm_size;
phys_addr_t l1tcm_phys;
struct list_head mtk_scp_list;
+
+ /* Prevent concurrent operations of L2TCM power control. */
+ struct mutex l2tcm_lock;
+ u32 l2tcm_refcnt;
};
/**
@@ -449,7 +453,7 @@ static int mt8192_scp_before_load(struct mtk_scp *scp)
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
- /* enable SRAM clock */
+ /* enable SRAM power */
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
@@ -462,19 +466,38 @@ static int mt8192_scp_before_load(struct mtk_scp *scp)
return 0;
}
-static int mt8195_scp_before_load(struct mtk_scp *scp)
+static int mt8195_scp_l2tcm_on(struct mtk_scp *scp)
{
- /* clear SPM interrupt, SCP2SPM_IPC_CLR */
- writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
+ struct mtk_scp_of_cluster *scp_cluster = platform_get_drvdata(scp->cluster_pdev);
+
+ mutex_lock(&scp_cluster->l2tcm_lock);
+
+ if (scp_cluster->l2tcm_refcnt == 0) {
+ /* clear SPM interrupt, SCP2SPM_IPC_CLR */
+ writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
+
+ /* Power on L2TCM */
+ scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
+ scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
+ scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
+ scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
+ MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
+ }
+
+ scp_cluster->l2tcm_refcnt += 1;
+ mutex_unlock(&scp_cluster->l2tcm_lock);
+
+ return 0;
+}
+
+static int mt8195_scp_before_load(struct mtk_scp *scp)
+{
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
+ mt8195_scp_l2tcm_on(scp);
+
/* enable SRAM clock */
- scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
- scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
- scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
- scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
- MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
/* enable MPU for all memory regions */
@@ -487,6 +510,8 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp)
{
scp->data->scp_reset_assert(scp);
+ mt8195_scp_l2tcm_on(scp);
+
scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0);
/* enable MPU for all memory regions */
@@ -653,14 +678,30 @@ static void mt8192_scp_stop(struct mtk_scp *scp)
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
}
+static void mt8195_scp_l2tcm_off(struct mtk_scp *scp)
+{
+ struct mtk_scp_of_cluster *scp_cluster = platform_get_drvdata(scp->cluster_pdev);
+
+ mutex_lock(&scp_cluster->l2tcm_lock);
+
+ scp_cluster->l2tcm_refcnt -= 1;
+
+ if (scp_cluster->l2tcm_refcnt == 0) {
+ /* Power off L2TCM */
+ scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
+ scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
+ scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
+ scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
+ scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
+ }
+
+ mutex_unlock(&scp_cluster->l2tcm_lock);
+}
+
static void mt8195_scp_stop(struct mtk_scp *scp)
{
- /* Disable SRAM clock */
- scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
- scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
- scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
- scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
- MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
+ mt8195_scp_l2tcm_off(scp);
+
scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
/* Disable SCP watchdog */
@@ -669,6 +710,8 @@ static void mt8195_scp_stop(struct mtk_scp *scp)
static void mt8195_scp_c1_stop(struct mtk_scp *scp)
{
+ mt8195_scp_l2tcm_off(scp);
+
/* Power off CPU SRAM */
scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0);
@@ -976,6 +1019,8 @@ static int scp_add_single_core(struct platform_device *pdev)
if (IS_ERR(scp))
return PTR_ERR(scp);
+ scp->cluster_pdev = pdev;
+
ret = rproc_add(scp->rproc);
if (ret) {
dev_err(dev, "Failed to add rproc\n");
@@ -1028,6 +1073,8 @@ static int scp_add_multi_core(struct platform_device *pdev)
goto init_fail;
}
+ scp->cluster_pdev = pdev;
+
ret = rproc_add(scp->rproc);
if (ret) {
dev_err(dev, "Failed to add rproc of core %d\n", core_id);
@@ -1114,6 +1161,7 @@ static int scp_probe(struct platform_device *pdev)
}
INIT_LIST_HEAD(&scp_cluster->mtk_scp_list);
+ mutex_init(&scp_cluster->l2tcm_lock);
platform_set_drvdata(pdev, scp_cluster);
ret = devm_of_platform_populate(dev);
@@ -1137,6 +1185,8 @@ static void scp_remove(struct platform_device *pdev)
rproc_del(scp->rproc);
scp_free(scp);
}
+
+ mutex_destroy(&scp_cluster->l2tcm_lock);
}
static const struct mtk_scp_of_data mt8183_of_data = {
--
2.18.0
