Add compatible name, clocks and update max reg items for SC7280
based platforms.
Add adsp-memory-regions property, required for memory sandboxing.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
---
Changes since V2:
-- Add clock property.
-- Add qcom,adsp-memory-regions property.
Changes since V1:
-- Change reg property maxItems to minItems and update description.
.../bindings/remoteproc/qcom,lpass-adsp-pil.yaml | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,lpass-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,lpass-adsp-pil.yaml
index 9f11332..45bc732 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,lpass-adsp-pil.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,lpass-adsp-pil.yaml
@@ -17,11 +17,13 @@ properties:
compatible:
enum:
- qcom,sdm845-adsp-pil
+ - qcom,sc7280-adsp-pil
reg:
- maxItems: 1
- description:
- The base address and size of the qdsp6ss register
+ minItems: 1
+ items:
+ - description: qdsp6ss register
+ - description: efuse q6ss register
interrupts:
items:
@@ -48,6 +50,7 @@ properties:
- description: QDSP XO clock
- description: Q6SP6SS SLEEP clock
- description: Q6SP6SS CORE clock
+ - description: GCC CFG NOC clock
clock-names:
items:
@@ -58,6 +61,7 @@ properties:
- const: qdsp6ss_xo
- const: qdsp6ss_sleep
- const: qdsp6ss_core
+ - const: gcc_cfg_noc
power-domains:
items:
@@ -77,6 +81,11 @@ properties:
maxItems: 1
description: Reference to the reserved-memory for the Hexagon core
+ qcom,adsp-memory-regions:
+ minItems: 1
+ items:
+ - description: List of memory regions accessed by ADSP firmware.
+
qcom,halt-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
--
2.7.4
