On 5/21/22 12:37 AM, Stephen Boyd wrote:
Quoting Sibi Sankar (2022-05-20 11:08:52)
Hey Bjorn,
Thanks for taking time to review the series.
On 5/20/22 2:05 AM, Bjorn Andersson wrote:
On Thu 19 May 09:47 PDT 2022, Sibi Sankar wrote:
Add interconnects that are required to be proxy voted upon during modem
bootup on SC7280 SoCs.
This looks reasonable, but how come the vote is only for DDR frequency?
What about the buses between modem and ddr?
The proxy votes that are put in aren't for perf related reasons, the
modem was getting llcc timeouts while trying to read contents from
memory. The hw team recommended the proxy votes as the fix.
Presumably the bootloader sets up some initial modem and ddr bus
bandwidth requests? Or the modem bootloader stage (MSA?) handles that
part?
Stephen/Bjorn,
Sorry for the delay, took a while to dig this up. The modem interconnect
is connected directly to gemnoc ddr. The path info from modem --> ddr is
split up into modem --> llcc and llcc --> ddr (Similar to CPUs) i.e. in
the end scaling of the path involves scaling of the two clocks, gemnoc
and ddr. There isn't any default vote for modem --> llcc as such but it
gets implicitly scaled when we vote max for llcc --> ddr path due to
dependency maintained between the two clocks by rpmh.
-Sibi
