On Tue 29 Dec 19:27 CST 2020, Martin Blumenstingl wrote: > Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4 > controller for always-on operations, typically used for managing system > suspend. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > --- > .../remoteproc/amlogic,meson-mx-ao-arc.yaml | 87 +++++++++++++++++++ > 1 file changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml > > diff --git a/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml > new file mode 100644 > index 000000000000..ba5deebaf7dc > --- /dev/null > +++ b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/remoteproc/amlogic,meson-mx-ao-arc.yaml#"; > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > + > +title: Amlogic Meson AO ARC Remote Processor bindings > + > +description: > + Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC core > + controller for always-on operations, typically used for managing > + system suspend. Meson6 and older use a ARC core based on the ARCv1 > + ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA) > + core. > + > +maintainers: > + - Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > + > +properties: > + compatible: > + items: > + - enum: > + - amlogic,meson8-ao-arc > + - amlogic,meson8b-ao-arc > + - const: amlogic,meson-mx-ao-arc > + > + firmware-name: > + $ref: /schemas/types.yaml#/definitions/string > + description: > + The name of the firmware which should be loaded for this remote > + processor. > + > + reg: > + description: > + Address ranges of the remap and CPU control addresses for the > + remote processor. > + minItems: 2 > + > + reg-names: > + items: > + - const: remap > + - const: cpu > + > + resets: > + minItems: 1 > + > + clocks: > + minItems: 1 > + > + sram: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + phandles to a reserved SRAM region which is used as the memory of > + the ARC core. The region should be defined as child nodes of the > + AHB SRAM node as per the generic bindings in > + Documentation/devicetree/bindings/sram/sram.yaml > + > + amlogic,secbus2: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + A phandle to the SECBUS2 region which contains some configuration > + bits of this remote processor > + > +required: > + - compatible > + - reg > + - reg-names > + - resets > + - clocks > + - sram > + - amlogic,secbus2 > + > +additionalProperties: false > + > +examples: > + - | > + remoteproc@1c { > + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; > + reg = <0x1c 0x8>, <0x38 0x8>; I'm generally not in favor of mapping "individual" registers, do you know what hardware block this is part of? Can you express the whole block as an single entity in your DT? Regards, Bjorn > + reg-names = "remap", "cpu"; > + resets = <&media_cpu_reset>; > + clocks = <&media_cpu_clock>; > + sram = <&ahb_sram_ao_arc>; > + amlogic,secbus2 = <&secbus2>; > + }; > + > +... > -- > 2.30.0 >
