On Thu, Oct 8, 2020 at 4:21 PM Ben Levinsky <BLEVINSK@xxxxxxxxxx> wrote: > As you said, this is just regular ARM TCM memory (as seen by the main ARM64 cluster). > Yes I can add back the compatible string, though maybe just "tcm" or "xlnx,tcm" I mean that if it is an ARM standard feature it should be prefixed "arm," > That being said, we can change this around to couple the TCM bank nodes into the R5 as we have In our present, internal implementation at > - https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/remoteproc/xilinx%2Czynqmp-r5-remoteproc.txt > - https://github.com/Xilinx/linux-xlnx/blob/master/drivers/remoteproc/zynqmp_r5_remoteproc.c > the TCM nodes are coupled in the R5 but after some previous review on this list, it was moved to have the TCM nodes decoupled from the R5 node > > I am not sure what you mean on the Arm64 handling of TCM memory. Via the architecture of the SoC https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf I know that the A53 cluster can see the absolute addresses of the R5 cluster so the translation is *I think* done as you describe with the CP15 instructions you listed. It seems like the TCM memories are von Neumann type (either can contain both code and data) which removes one of my worries. According to this data sheet they are also nothing ARM-provided but a Xilinx invention, and just happen to be hardcoded at the same address as TCM memories in ARM32, what a coincidence. So I take it this is the correct view and you can proceed like this, sorry for the fuzz. Yours, Linus Walleij
