This adds the support of APU to mt8183.
Signed-off-by: Alexandre Bailon <abailon@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 39 ++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index e215f1eb3eb2..28f75452961c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -967,12 +967,51 @@ ipu_adl: syscon@19010000 {
#clock-cells = <1>;
};
+ apu0: apu@0x19100000 {
+ compatible = "mediatek,mt8183-apu";
+ reg = <0 0x19180000 0 0x14000>;
+ interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_LOW>;
+
+ iommus = <&iommu M4U_PORT_IMG_IPUO>,
+ <&iommu M4U_PORT_IMG_IPU3O>,
+ <&iommu M4U_PORT_IMG_IPUI>;
+
+ clocks = <&ipu_core0 CLK_IPU_CORE0_AXI>,
+ <&ipu_core0 CLK_IPU_CORE0_IPU>,
+ <&ipu_core0 CLK_IPU_CORE0_JTAG>;
+
+ clock-names = "axi", "ipu", "jtag";
+
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_VPU_CORE0>;
+ status = "disabled";
+ };
+
ipu_core0: syscon@19180000 {
compatible = "mediatek,mt8183-ipu_core0", "syscon";
reg = <0 0x19180000 0 0x1000>;
#clock-cells = <1>;
};
+ apu1: apu@19200000 {
+ compatible = "mediatek,mt8183-apu";
+ reg = <0 0x19280000 0 0x14000>;
+ interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_LOW>;
+
+ iommus = <&iommu M4U_PORT_CAM_IPUO>,
+ <&iommu M4U_PORT_CAM_IPU2O>,
+ <&iommu M4U_PORT_CAM_IPU3O>,
+ <&iommu M4U_PORT_CAM_IPUI>,
+ <&iommu M4U_PORT_CAM_IPU2I>;
+
+ clocks = <&ipu_core0 CLK_IPU_CORE1_AXI>,
+ <&ipu_core0 CLK_IPU_CORE1_IPU>,
+ <&ipu_core0 CLK_IPU_CORE1_JTAG>;
+
+ clock-names = "axi", "ipu", "jtag";
+
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_VPU_CORE1>;
+ };
+
ipu_core1: syscon@19280000 {
compatible = "mediatek,mt8183-ipu_core1", "syscon";
reg = <0 0x19280000 0 0x1000>;
--
2.26.2
