On Sat, 16 Nov 2019 18:08:43 +0100, Paul Cercueil wrote: > Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from > Ingenic is a second Xburst MIPS CPU very similar to the main core. > This document describes the devicetree bindings for this auxiliary > processor. > > Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx> > --- > > Notes: > v2: Update TCSM0 address in example > v3: Change node name to 'video-decoder' > > .../bindings/remoteproc/ingenic,vpu.txt | 36 +++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 Documentation/devicetree/bindings/remoteproc/ingenic,vpu.txt > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
