On Mon, Jan 04, 2021 at 02:35:15PM +0800, Weihang Li wrote: > From: Yangyang Li <liyangyang20@xxxxxxxxxx> > > In order to improve performance by balancing the load between different > banks of cache, the CQC cache is desigend to choose one of 4 banks > according to lower 2 bits of CQN. The hns driver needs to count the number > of CQ on each bank and then assigns the CQ being created to the bank with > the minimum load first. > > Signed-off-by: Yangyang Li <liyangyang20@xxxxxxxxxx> > Signed-off-by: Weihang Li <liweihang@xxxxxxxxxx> > --- > drivers/infiniband/hw/hns/hns_roce_cq.c | 114 +++++++++++++++++++++++----- > drivers/infiniband/hw/hns/hns_roce_device.h | 10 ++- > drivers/infiniband/hw/hns/hns_roce_main.c | 8 +- > 3 files changed, 104 insertions(+), 28 deletions(-) > > diff --git a/drivers/infiniband/hw/hns/hns_roce_cq.c b/drivers/infiniband/hw/hns/hns_roce_cq.c > index 8533fc2..00350a3 100644 > --- a/drivers/infiniband/hw/hns/hns_roce_cq.c > +++ b/drivers/infiniband/hw/hns/hns_roce_cq.c > @@ -38,11 +38,74 @@ > #include "hns_roce_hem.h" > #include "hns_roce_common.h" > <...> > + id = ida_alloc_range(&bank->ida, bank->min, bank->max, GFP_ATOMIC); Do you create CQ in atomic context? It is probably GFP_KERNEL and not GFP_ATOMIC. Thanks
