Stash is a mechanism that uses the core information carried by the ARM AXI bus to access the L3 cache. The CPU and I/O subsystems can access the L3 cache consistently by enabling stash, so the performance can be improved. Changes since v3: - Add strcuture name as a parameter when defining a field, the hr_reg_enable() will check the type and cast the array to __le32 *. - Fix the alignment style of CQC and QPC structure. Changes since v2: - Replace hr_reg_set() with hr_reg_enable(), which supports to set a single bit. Changes since v1: - Fix comments from Jason about the unused macros. - Rewrite hr_reg_set() to make it easier for driver to define and set a field. Previous versions: v3: https://patchwork.kernel.org/project/linux-rdma/cover/1605867440-2413-1-git-send-email-liweihang@xxxxxxxxxx/ v2: https://patchwork.kernel.org/project/linux-rdma/cover/1605527919-48769-1-git-send-email-liweihang@xxxxxxxxxx/ v1: https://patchwork.kernel.org/project/linux-rdma/cover/1601458452-55263-1-git-send-email-liweihang@xxxxxxxxxx/ Lang Cheng (2): RDMA/hns: Add support for CQ stash RDMA/hns: Add support for QP stash drivers/infiniband/hw/hns/hns_roce_common.h | 12 ++ drivers/infiniband/hw/hns/hns_roce_device.h | 1 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 9 ++ drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 167 +++++++++++++++------------- 4 files changed, 112 insertions(+), 77 deletions(-) -- 2.8.1
