On Fri, Sep 18, 2020 at 6:07 PM Jason Gunthorpe <jgg@xxxxxxxx> wrote: > > On Fri, Sep 18, 2020 at 05:45:21PM +0300, Oded Gabbay wrote: > > > Any access by the device's engines to the host memory is done via our > > device's MMU. Our MMU supports multiple ASIDs - Address Space IDs. The > > kernel driver is assigned ASID 0, while the user is assigned ASID 1. > > We can support up to 1024 ASIDs, but because we limit the user to have > > a single application, we only use ASID 0 and 1. > > If the QP/WQ/etc is HW bound to an ASID then that binding is called a > PD and the ASID is acting in the PD role. > > If the ASID is translating from on the wire IOVA to DMA PA, then it is > acting in the MR role as well. > > Bundling those two things together is not as flexible as standards > based RDMA, but it is not as far away as you are making things out to > be. > > Jason But Jason, why do I need to use RDMA definitions in my common code ? RDMA is such a small part of our ASIC. We also have an ASIC called GOYA for inference, which is handled by the same driver, but doesn't have RDMA ports at all. Why would I need to use RDMA definitions for that ? I'm sorry, but you won't be able to convince me here that I need to "enslave" my entire code to RDMA, just because my ASIC "also" has some RDMA ports. On the same weight, the GPU people tried and failed to say that my device is a GPU. And I think the reasoning that we applied back then, and Greg and Olof agreed with it, applies here as well. I want to play along, but it has to be something that won't make my entire device's driver into an RDMA driver. And it has to be something that doesn't hurt performance. All other things can and will be changed according to your inputs. Thanks, Oded Oded
