On Tue, Jun 30, 2020 at 05:21:33PM +0000, Xiong, Jianxin wrote: > > > Heterogeneous Memory Management (HMM) utilizes mmu_interval_notifier > > > and ZONE_DEVICE to support shared virtual address space and page > > > migration between system memory and device memory. HMM doesn't support > > > pinning device memory because pages located on device must be able to > > > migrate to system memory when accessed by CPU. Peer-to-peer access is > > > possible if the peer can handle page fault. For RDMA, that means the > > > NIC must support on-demand paging. > > > > peer-peer access is currently not possible with hmm_range_fault(). > > Currently hmm_range_fault() always sets the cpu access flag and device > private pages are migrated to the system RAM in the fault handler. However, > it's possible to have a modified code flow to keep the device private page info > for use with peer to peer access. Sort of, but only within the same device, RDMA or anything else generic can't reach inside a DEVICE_PRIVATE and extract anything useful. > > So.. this patch doesn't really do anything new? We could just make a MR against the DMA buf mmap and get to the same place? > > That's right, the patch alone is just half of the story. The functionality > depends on availability of dma-buf exporter that can pin the device > memory. Well, what do you want to happen here? The RDMA parts are reasonable, but I don't want to add new functionality without a purpose - the other parts need to be settled out first. The need for the dynamic mapping support for even the current DMA Buf hacky P2P users is really too bad. Can you get any GPU driver to support non-dynamic mapping? > > > migrate to system RAM. This is due to the lack of knowledge about > > > whether the importer can perform peer-to-peer access and the lack of > > > resource limit control measure for GPU. For the first part, the latest > > > dma-buf driver has a peer-to-peer flag for the importer, but the flag > > > is currently tied to dynamic mapping support, which requires on-demand > > > paging support from the NIC to work. > > > > ODP for DMA buf? > > Right. Hum. This is not actually so hard to do. The whole dma buf proposal would make a lot more sense if the 'dma buf MR' had to be the dynamic kind and the driver had to provide the faulting. It would not be so hard to change mlx5 to be able to work like this, perhaps. (the locking might be a bit tricky though) > > > There are a few possible ways to address these issues, such as > > > decoupling peer-to-peer flag from dynamic mapping, allowing more > > > leeway for individual drivers to make the pinning decision and adding > > > GPU resource limit control via cgroup. We would like to get comments > > > on this patch series with the assumption that device memory pinning > > > via dma-buf is supported by some GPU drivers, and at the same time > > > welcome open discussions on how to address the aforementioned issues > > > as well as GPU-NIC peer-to-peer access solutions in general. > > > > These seem like DMA buf problems, not RDMA problems, why are you asking these questions with a RDMA patch set? The usual DMA buf > > people are not even Cc'd here. > > The intention is to have people from both RDMA and DMA buffer side to > comment. Sumit Semwal is the DMA buffer maintainer according to the > MAINTAINERS file. I agree more people could be invited to the discussion. > Just added Christian Koenig to the cc-list. Would be good to have added the drm lists too > If the umem_description you mentioned is for information used to create the > umem (e.g. a structure for all the parameters), then this would work better. It would make some more sense, and avoid all these weird EOPNOTSUPPS. Jason
