Hello Raed Salem,
The patch 7dfee4b1d79e: "net/mlx5: IPsec, Refactor SA handle creation
and destruction" from Oct 23, 2019, leads to the following static
checker warning:
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c:711 mlx5_fpga_ipsec_create_sa_ctx()
warn: bitwise AND condition is false here
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c
701 sizeof(sa_ctx->hw_sa))) {
702 context = ERR_PTR(-EINVAL);
703 goto exists;
704 }
705
706 ++fpga_xfrm->num_rules;
707 context = fpga_xfrm->sa_ctx;
708 goto exists;
709 }
710
711 if (accel_xfrm->attrs.action & MLX5_ACCEL_ESP_ACTION_DECRYPT) {
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This is zero and it's always used like this, so it can never be true.
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c:762 mlx5_fpga_ipsec_create_sa_ctx() warn: bitwise AND condition is false here
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c:856 mlx5_fpga_ipsec_release_sa_ctx() warn: bitwise AND condition is false here
712 err = ida_simple_get(&fipsec->halloc, 1, 0, GFP_KERNEL);
713 if (err < 0) {
714 context = ERR_PTR(err);
715 goto exists;
716 }
717
718 sa_ctx->sa_handle = err;
719 if (sa_handle)
720 *sa_handle = sa_ctx->sa_handle;
721 }
722 /* This is unbounded fpga_xfrm, try to add to hash */
723 mutex_lock(&fipsec->sa_hash_lock);
724
725 err = rhashtable_lookup_insert_fast(&fipsec->sa_hash, &sa_ctx->hash,
regards,
dan carpenter
