From: James Erwin <james.erwin@xxxxxxxxx>
If an hfi1 card is inserted in a Gen4 systems, the driver will avoid
the gen3 speed bump and the card will operate at half speed.
This is because the driver avoids the gen3 speed bump when the parent
bus speed isn't identical to gen3, 8.0GT/s. This is not
compatible with gen4 and newer speeds.
Fix by relaxing the test to explicitly look for the lower
capability speeds which inherently allows for gen4 and all future
speeds.
Fixes: 7724105686e7 ("IB/hfi1: add driver files")
Cc: <stable@xxxxxxxxxxxxxxx>
Reviewed-by: Dennis Dalessandro <dennis.dalessandro@xxxxxxxxx>
Reviewed-by: Kaike Wan <kaike.wan@xxxxxxxxx>
Signed-off-by: James Erwin <james.erwin@xxxxxxxxx>
Signed-off-by: Mike Marciniszyn <mike.marciniszyn@xxxxxxxxx>
Signed-off-by: Dennis Dalessandro <dennis.dalessandro@xxxxxxxxx>
---
drivers/infiniband/hw/hfi1/pcie.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index 61aa550..61362bd 100644
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -319,7 +319,9 @@ int pcie_speeds(struct hfi1_devdata *dd)
/*
* bus->max_bus_speed is set from the bridge's linkcap Max Link Speed
*/
- if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) {
+ if (parent &&
+ (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT ||
+ dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) {
dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n");
dd->link_gen3_capable = 0;
}
