On Tue, Oct 22, 2019 at 05:09:19PM +0000, Jason Gunthorpe wrote: > On Tue, Oct 22, 2019 at 01:06:31PM -0400, Jerome Glisse wrote: > > > > > That is fine, the device driver should not do anything with it ie > > > > if the device driver wanted to write then the write fault test > > > > would return true and it would fault. > > > > > > > > Note that driver should not dereference the struct page. > > > > > > Can this thing be dma mapped for read? > > > > > > > Yes it can, the zero page is just a regular page (AFAIK on all > > architecture). So device can dma map it for read only, there is > > no reason to treat it any differently. > > > > The HMM_PTE_SPECIAL is only (as documented in the header) for > > pte insert with insert_pfn or insert_page ie pte inserted in > > vma with MIXED or PFNMAP flag. While HMM catch those vma early > > on and backof it can still race with some driver setting the vma > > flag and installing special pte afterward hence why special pte > > goes through this special path. > > > > The zero page being a special pte is just an exception ie it > > is the only special pte allowed in vma that do not have MIXED or > > PFNMAP flag set. > > Just to be clear then, the correct behavior is to return the zero page > pfn as a HMM_PFN_VALID and the driver should treat it the same as any > memory page and dma map it? Yes correct. > > Smart drivers can test somehow for pfn == zero_page and optimize? There is nothing to optimize here, i do not know any hardware that have a special page table entry that make all memory access return zero. What was confusing in Ralph commit message is that he was conflating the memory migration, which is a totaly different code path, with that code. When doing memory migration it is easy to program the DMA engine to zero out destination memory (common feature found on various devices) and that optimization is allowed by the migrate code. So i can not think of any reason why distinguishing the zero page in this code would help. Maybe i missed some new feature in the mmu of some new hardware. Cheers, Jérôme
