Hello Sagi, Christoph, Bart, Jason, Doug, Leon and Co
This patchset adds a new verbs API for T10-PI offload and
implementation for iSER initiator (NVMe-oF/RDMA host side was completed
and will be sent on a different patchset).
This set starts with a few preparation commits to the RDMA/core layer.
It continues with introducing a new MR type IB_MR_TYPE_PI. Using this MR
all the needed mappings will be done in the low level drivers and not
be visible to the ULP. Later patches implement the needed functionality
in the mlx5 layer. As suggested by Sagi, in the new API, the mlx5 driver
will allocate a single internal memory region for the UMR operation to
register both PI and data SG lists and it will look like:
data start meta start
| |
-------------------------
|d1|d2|d3|d4|m1|m2|m3|m4|
-------------------------
The sig_mr stride block would be using the same lkey but different
offsets in it (offset 0 and offset d1+d2+d3+d4). The verbs layer will
use a special mr type that will describe everything and will replace
the old API, that enforce using 3 different memory regions (data_mr,
protection_mr, sig_mr) and their local invalidations. This will ease
the code in the ULP and will improve the abstraction of the HW (see
iSER code changes).
The patchset ends with iSER initator patches that using this new API.
The code was tested vs. LIO iSER target using Mellanox's ConnectX-4/ConnectX-5.
This series applies cleanly on top of kernel 5.0-rc3 tag and iser fix
("efa423925cd4 IB/iser: Pass the correct number of entries for dma mapped SGL").
We should aim to push this code during 5.1 merge window.
Guys this looks very good (from an very high level peek)! I've yet to
look into this but its most certainly a welcome improvement.
