From: Michael J. Ruhl <michael.j.ruhl@xxxxxxxxx>
HFI IRQ enable bits are not being set correctly. Send context error
and DC IRQs are not being enabled correctly. In addition, send
context error IRQs are not being delivered.
Because of this, send context errors are not being handled correctly
when they occur.
When setting the IRQ bits, if an IRQ range is used, and the last bit
is on a register boundary (bit 63), the calculated index for the
final register modification is incorrect (index + 1 vs. index).
The incorrect index calculation causes incorrect IRQ bits to be set.
In this case the send context error IRQ is NOT enabled.
Fix by using the 'last' value rather than the counted 'src' value to
determine the final index to use. This satisfies all cases.
Fixes: a2f7bbdc2dba ("IB/hfi1: Rework the IRQ API to be more flexible")
Reviewed-by: Mike Marciniszyn <mike.marciniszyn@xxxxxxxxx>
Reviewed-by: Dennis Dalessandro <dennis.dalessandro@xxxxxxxxx>
Signed-off-by: Michael J. Ruhl <michael.j.ruhl@xxxxxxxxx>
Signed-off-by: Dennis Dalessandro <dennis.dalessandro@xxxxxxxxx>
---
drivers/infiniband/hw/hfi1/chip.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c
index ef433fd..290c3b5 100644
--- a/drivers/infiniband/hw/hfi1/chip.c
+++ b/drivers/infiniband/hw/hfi1/chip.c
@@ -13012,7 +13012,7 @@ int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set)
}
bits |= BIT_ULL(bit);
}
- read_mod_write(dd, src, bits, set);
+ read_mod_write(dd, last, bits, set);
return 0;
}
