On Thu, Jun 21, 2018 at 03:37:55PM +0300, Leon Romanovsky wrote:
> From: Talat Batheesh <talatb@xxxxxxxxxxxx>
>
> Add capability bit in PCAM register and RoCE ICRC error counter
> to PPCNT register.
>
> Signed-off-by: Talat Batheesh <talatb@xxxxxxxxxxxx>
> Reviewed-by: Mark Bloch <markb@xxxxxxxxxxxx>
> Signed-off-by: Leon Romanovsky <leonro@xxxxxxxxxxxx>
> ---
> include/linux/mlx5/mlx5_ifc.h | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
> index b4302ccb63a6..9e8682489951 100644
> --- a/include/linux/mlx5/mlx5_ifc.h
> +++ b/include/linux/mlx5/mlx5_ifc.h
> @@ -1687,7 +1687,11 @@ struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
>
> u8 rx_buffer_full_low[0x20];
>
> - u8 reserved_at_1c0[0x600];
> + u8 rx_icrc_encapsulated_high[0x20];
> +
> + u8 rx_icrc_encapsulated_low[0x20];
> +
> + u8 reserved_at_3c0[0x5c0];
reserved_at_3c0 should be reserved_at_200, fixed and applied to mlx5-next.
Commit 0af5107cd0640ee3424e337b492e4b11b450ce28 in mlx5-next.
Thanks
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