On Tue, May 22, 2018 at 08:47:17PM +0800, Lijun Ou wrote:
> In post send verb, The doorbell array is used for storing sq db temporarily
> and the fields of sq db is __le32. As a result, the doorbell array should
> be __le32.
>
> Signed-off-by: Lijun Ou <oulijun@xxxxxxxxxx>
> drivers/infiniband/hw/hns/hns_roce_device.h | 2 +-
> drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 6 +++---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
> index fb305b7..3b34c50 100644
> +++ b/drivers/infiniband/hw/hns/hns_roce_device.h
> @@ -850,7 +850,7 @@ static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp)
> return container_of(hr_qp, struct hns_roce_sqp, hr_qp);
> }
>
> -static inline void hns_roce_write64_k(__be32 val[2], void __iomem *dest)
> +static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
> {
> __raw_writeq(*(u64 *) val, dest);
> }
This is nonsense. The driver needs to use writeq directly and not
mangle le32/be32 like this. __raw_writeq is only for platform specific
driver use.
Register writes to PCI-E MMIO space should not have an endianness as
writeq takes care of all required swapping from host -> PCI-E to give
a consistent TLP on all platforms.
So the correct thing is to make a u64 with the proper layout and pass
that directly to writeq.
eg probably
writeq(((u64)le32_to_cpu(sq_db.u32_4) << 32) |
le32_to_cpu(sq_db.u32_8))
Same general statements are true of the __raw_writel/readl I see...
Please send a patch fixing all of this this properly.
Jason
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