On Tue, Apr 17, 2018 at 03:56:13PM +0000, Marciniszyn, Mike wrote: > > > > Btw, why is the driver configuring the PCIe link speed? Isn't this > > something we should be handling in the PCI core? > > The device comes out of reset at the 5GT/s speed. The driver > downloads device firmware, programs PCIe registers, and co-ordinates > the transition to 8GT/s. > > This recipe is device specific and is therefore implemented in the > hfi1 driver built on top of PCI core functions and macros. Do you think this behavior conforms to the spec, or is this a workaround for a hardware erratum? I don't think it's feasible to have every driver deal with this level of PCIe detail. Do you have to do something similar in the Windows driver? Is there something we can do in the PCI core to do the reconfiguration? If you can't go to 8GT/s before doing some device-specific initialization, could the driver do that setup and then use a generic PCI core interface to reconfigure the link? Or maybe if the driver finds the device at 5GT/s, it could download the firmware and reset the device. Would the device then negotiate at 8GT/s? Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
