Please don't top post, write shorter lines, and add the odd blank line. Big blocks of text are hard to read quickly. > From: Petrosyan, Ludwig [mailto:ludwig.petrosyan@xxxxxxx] > Yes I agree it has to be started with the write transaction, according of PCIe standard all write > transaction are address routed, and I agree with Logan: > if in write transaction TLP the endpoint address written in header the TLP should not touch CPU, the > PCIe Switch has to route it to endpoint. That depends, IIRC there is a feature for PCIe switches to force them to send all transactions to the root hub. This is there so that the host can enforce rules to stop p2p transfers. It might enabled on the switch you have. > The idea was: in MTCA system there is PCIe Switch on MCH (MTCA crate HUB) this switch connects CPU to > other Crate Slots, so one port is Upstream and others are Downstream ports, DMA read from CPU is > usual write on endpoint side, Xilinx DMA core has two registers Destination Address and Source > Address, > device driver to make DMA has to set up these registers, > usually device driver to start DMA read from Board sets Source address as FPGA memory address and > Destination address is DMA prepared system address, > in case of testing p2p I set Destination address as physical address of other endpoint. Unnecessary detail... > More detailed: > we have so called pcie universal driver: the idea behind is > 1. all pcie configuration staff, find enabled BARs, mapping BARs, usual read/write and common ioctl > (get slot number, get driver version ...) implemented in universal driver and EXPORTed. > 2. if some system function in new kernel are changed we change it only in universal parts (easy > support a big number of drivers ) > so the universal driver something like PCIe Driver API > 3. the universal driver provides read/writ functions so we have the same device access API for any > PCIe device, we could use the same user application with any PCIe device More crap... > now. during BARs finding and mapping universal driver keeps pcie endpoint physical address in some > internal structures, any top driver may get physical address > of other pcie endpoint by slot number. > in may case during get_resorce the physical address is 0xB2000000, I check lspci -H1 -vvvv -s psie > switch port bus address (the endpoint connected to this port, checked by lspci -H1 -t) the same > address (0xB200000) is the memory behind bridge, Overly verbose... > I want to make p2p writes to offset 0x40000, so I set DMA destination address 0xB2400000 > is something wrong? Possibly. You almost certainly need the address that is written into the BAR of the target endpoint. This could well be different from the physical address that the cpu uses to write to the endpoint (as well as the cpu virtual address). lspci lies [1], run lspci -x (or hexdump config space through /sys/devices) to see what is actually in the BAR. [1] The addresses come from somewhere other than reading the BAR. If the endpoint resets the BAR lspci will still report the old addresses. David ��.n��������+%������w��{.n�����{���fk��ܨ}���Ơz�j:+v�����w����ޙ��&�)ߡ�a����z�ޗ���ݢj��w�f
