On Wed, Sep 06, 2017 at 09:18:58AM +0000, Amrani, Ram wrote:
> > On Tue, Sep 05, 2017 at 05:36:54PM +0300, Ram Amrani wrote:
> > > + if (iwarp) {
> > > + writel(qp->rq.iwarp_db2_data.raw, qp->rq.iwarp_db2);
> > > + mmio_flush_writes();
> > > + }
> >
> > Can you update this driver to use the macros in util/mmio.h and
> > discard this writel thing?
>
> Sure. I can write a dedicated patch to convert all of the locations at once.
>
> A couple of questions -
>
> I see that for 16, as an example, there are three functions:
> 1) mmio_write16_le()
> 2) mmio_write16_be()
> 3) mmio_write16()
> Per my understanding the first two do not manipulate the data and are only intended to
> allow sparse to pass (and protect us).
Yes..
> However the 3rd performs htole. Is this correct?
Yes, if necessary it performs the swap to create the defined TLP on
any arches that require it.
It is basically equivalent to the kernel's writel_relaxed
> #define MAKE_WRITE(_NAME_, _SZ_) \
> static inline void _NAME_##_be(void *addr, __be##_SZ_ value) \
> { \
> atomic_store_explicit((_Atomic(uint##_SZ_##_t) *)addr, \
> (__force uint##_SZ_##_t)value, \
> memory_order_relaxed); \
> } \
> What is the effect of the "relaxed ordering" if we use a non-WC BUS?
memory_order_relaxed tells the compiler to WRITE_ONCE but otherwise
not concern it self with ordering of stores.
eg
*foo = 1
mmio_write16(bar, 12);
Can be freely re-ordered during compilation and during execution.
Code needs to insert a util/barrier.h if it requires ordering.
But qedr is using WC right?
Jason
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