On 5/29/2017 1:05 PM, Leon Romanovsky wrote:
On Sun, May 28, 2017 at 12:53:00PM +0300, Max Gurtovoy wrote:
On 5/28/2017 12:07 PM, Christoph Hellwig wrote:
On Sun, May 28, 2017 at 10:53:11AM +0300, Max Gurtovoy wrote:
Cache the needed umr_fence and set the wqe ctrl segmennt
accordingly.
Looks good,
Reviewed-by: Christoph Hellwig <hch@xxxxxx>
Thanks.
But that whole fence logic looks awkward to me. Does the following
patch to reorder it make sense to you?
Yes it make sense to me.
Sagi/Leon, any comments ?
Max,
Do you see any performance impact for IB_WR_RDMA_READ, IB_WR_RDMA_WRITE
and IB_WR_RDMA_WRITE_WITH_IMM flows? They don't need fences and such
change can cause to performance losses.
Thanks
We don't fence those WR's.
Christoph just re-write it to be more intuitive code. I don't see logic
difference, am I wrong here ?
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