On Thu, Mar 09, 2017 at 04:59:40PM -0700, Stephen Warren wrote: > However, when I run the same test on a (non-cache-coherent) AArch64 (ARMv8) > machine (Cortex-A57, NVIDIA Tegra), the application does not work. In > particular, ivc_poll_cq() returns -2 when the application waits for an > ibv_post_send/recv() to complete. User space verbs are not supported on non-cache-coherent architectures for kernel bypass adapters and probably never will be. Ideally the kernel would not create the uverbs device for DMA drivers on such architectures.. Is there a kernel API to detect cache incoherence? > than e.g. the kernel filling in the CQ), and there don't appear to be any > cache invalidation operations anywhere in libmlx4 (I'm not even sure if > cache manipulation is possible from user-space on ARM). I also > couldn't find Precisely. Jason -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
