RE: [PATCH rdma-core 03/14] cxgb3: Update to use new udma write barriers

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> Steve says the chip reads until a EOP marked WR is found, so the only
> write barrier is to make sure DMA is ready before setting the WR in
> that way.
> 
> Add missing rmb()s in the obvious spot.
> 
> Signed-off-by: Jason Gunthorpe <jgunthorpe@xxxxxxxxxxxxxxxxxxxx>
> ---
>  providers/cxgb3/cq.c      | 2 ++
>  providers/cxgb3/cxio_wr.h | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/providers/cxgb3/cq.c b/providers/cxgb3/cq.c
> index a6158ce771f89f..eddcd43dc3bd8e 100644
> --- a/providers/cxgb3/cq.c
> +++ b/providers/cxgb3/cq.c
> @@ -121,6 +121,7 @@ static inline int cxio_poll_cq(struct t3_wq *wq, struct
t3_cq
> *cq,
> 
>  	*cqe_flushed = 0;
>  	hw_cqe = cxio_next_cqe(cq);
> +	udma_from_device_barrier();
> 
>  	/*
>  	 * Skip cqes not affiliated with a QP.
> @@ -266,6 +267,7 @@ static int iwch_poll_cq_one(struct iwch_device *rhp,
struct
> iwch_cq *chp,
>  	int ret = 1;
> 
>  	hw_cqe = cxio_next_cqe(&chp->cq);
> +	udma_from_device_barrier();
> 
>  	if (!hw_cqe)
>  		return 0;

Hey Jason, is it possible the omission on these was never detected because the
memory for cq (and sq and rq) queues is allocated in the kernel by
dma_alloc_coherent(), and mapped to the process's address space?  I'm wondering
how cxgb3 made it 10+ years this this bug...

Steve.



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