On Thu, Sep 29, 2016 at 04:28:02PM -0600, Jason Gunthorpe wrote:
> In the kernel the swapping behavior of 'writel' is architecture (and
> sometimes even platform) specific. Looking at the kernel headers
> suggests that BE PPC needs an explicit swap and BE ARM does not (eg
> the hardware swaps). Maybe. There are a lot of layers of macros in
> this area..
read{s,l,q} and write{s,l,q} in the kernel always perform an implicit
bytestap, that is the device is expected to use a LE layout. This
is not architecture specific, otherwise hell would break lose.
If the device has a BE layout you'll need to use ioread*be/iowrite*be
instead.
But none of this has an affect on userspace mappings of registers, as
those don't go through the kernel read{s,l,q} and write{s,l,q} helpers,
so if you mmap the resource directly your need to manually byte swap
to whatever the hardware expects - which seems to be LE for Chelsio
and BE for Mellanox.
Btw, one thing that would be useful is to introduce endiane annoatations
for sparse in rdma-core. I've added these to a few userspace projects
already, here is the most recent example:
https://github.com/linux-nvme/nvme-cli/commit/126b8beb35b76fe9f61b137e34aea66b64c07b25
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