On 10/07/2015 02:20 AM, Christoph Hellwig wrote:
On Tue, Oct 06, 2015 at 11:37:40AM +0300, Sagi Grimberg wrote:
The issue is that the device requires the MR page array to have
an alignment (0x40 for mlx4 and 0x400 for mlx5). When I modified the
page array allocation to be non-coherent I didn't take care of
alignment.
Just curious: why did you switch away from the coheret dma allocations
anyway? Seems like the page lists are mapped as long as they are
allocated so the coherent allocator would seem like a nice fit.
Hello Christoph,
My concern is that caching and/or write combining might be disabled for
DMA coherent memory regions. This is why I assume that calling
dma_map_single() and dma_unmap_single() will be faster for registering
multiple pages as a single memory region instead of using DMA coherent
memory.
Bart.
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