On Fri, Nov 24, 2023 at 08:23:52AM -0400, Jason Gunthorpe wrote: > On Fri, Nov 24, 2023 at 10:16:15AM +0000, Mark Rutland wrote: > > On Thu, Nov 23, 2023 at 09:04:31PM +0200, Leon Romanovsky wrote: > > > From: Jason Gunthorpe <jgg@xxxxxxxxxx> [...] > > > Provide a new generic function memcpy_toio_64() which should reliably > > > generate the needed instructions for the architecture, assuming address > > > alignment. As the usual need for this operation is performance sensitive a > > > fast inline implementation is preferred. > > > > There is *no* architectural sequence that is guaranteed to reliably generate a > > 64-byte TLP, and this sequence won't guarnatee that (e.g. even if the CPU > > *always* merged adjacent stores, we can take an interrupt mid-sequence that > > would prevent that). > > WC is not guaranteed on any arch, that is well known. > > The HW has means to handle fragmented TLPs, it just hurts performance > when it happens. "reliable" here means we'd like to see something like > a > 90% chance of the large TLP instead of the < 1% chance with the C > loop. > > Future ARM CPUs have the ST64B instruction which does provide the > architectural guarantee, and x86 has a similar guaranteed instruction > now too. > > > What's the actual requirement here? Is this just for performance? > > Yes, just performance. Do you have any rough numbers (percentage)? It's highly microarchitecture-dependent until we get the ST64B instruction. More of a bike-shedding, I wonder whether the __iowrite*_copy() semantics are better suited for what you need in terms of ordering (not that mempcy_toio() to Normal NC memory gives us any ordering). -- Catalin
