> On Fri, 10 Feb 2023 16:40:47 +0530 Hariprasad Kelam wrote: > > octeontx2 silicon and CN10K transmit interface consists of five > > transmit levels starting from MDQ, TL4 to TL1. Once packets are > > submitted to MDQ, hardware picks all active MDQs using strict > > priority, and MDQs having the same priority level are chosen using > > round robin. Each packet will traverse MDQ, TL4 to TL1 levels. > > Each level contains an array of queues to support scheduling and > > shaping. > > > > As HTB supports classful queuing mechanism by supporting rate and ceil > > and allow the user to control the absolute bandwidth to particular > > classes of traffic the same can be achieved by configuring shapers and > > schedulers on different transmit levels. > > Please provide or link to some user-facing documentation under > Documentation/networking/device_drivers/ethernet/marvell/octeon... ACK, will add in next version.
