From: Saeed Mahameed <saeedm@xxxxxxxxxx>
This series includes various mlx5 updates
1) HW definitions and support for NPPS clock settings.
2) NVMEoTCP HW capabilities and definitions
3) crypt HW bits and definitions for upcoming ipsec and TLS improvements
4) various cleanups
5) Enable hash mode by default for all NICs
Liu, Changcheng Says:
=====================
When hardware lag hash mode is active, the explicit port affinity
of the QP/TIS is ignored. The steering rules inside the port-select
steering domain will determine the egress port.
To support setting explicit port affinity while using hardware lag
hash mode, a new capability of bypassing the port-select steering
domain is introduced.
The following patch series enable hash mode over NICs that support
the new capability:
5.1) Set the active port bit mask to let the firmware know which ports
are down and which are up, so it can use this info when handling
failover on QPs with explicit port affinity.
5.2) Remove the assignment of default port affinity by the driver as
the user has dedicated userspace APIs to set the port affinity so
the default configuration isn't needed anymore.
5.3) Detect and enable port-select bypass so explicit port affinity is
honored by the firmware.
5.4) Enable hash mode by default on all NICs
When setting QP/TIS port affinity explicitly and hash mode is active
and the bypass port-select flow table capability is enabled by firmware,
firmware adds a steering rule to catch egress traffic of these QPs/TISs
and make their traffic skip the port-select steering domain. This adds
performance overhead for all QPs/TISs. The common use case is to not
set explicit port affinity(as when in hash, we don't need it). If there
is a user that does want to set port affinity, it can be done with the
dedicated userspace APIs.
Detect the bypass port-select flow table capability, set it to let
firmware know the driver supports this new capability.
=====================
Aya Levin (2):
net/mlx5: Expose NPPS related registers
net/mlx5: Add support for NPPS with real time mode
Ben Ben-Ishay (1):
net/mlx5: Add NVMEoTCP caps, HW bits, 128B CQE and enumerations
Gal Pressman (2):
net/mlx5: Remove unused functions
net/mlx5: Remove unused structs
Jianbo Liu (2):
net/mlx5: Add IFC bits for general obj create param
net/mlx5: Add IFC bits and enums for crypto key
Leon Romanovsky (1):
net/mlx5: Remove from FPGA IFC file not-needed definitions
Liu, Changcheng (5):
net/mlx5: add IFC bits for bypassing port select flow table
RDMA/mlx5: Don't set tx affinity when lag is in hash mode
net/mlx5: Lag, set active ports if support bypass port select flow
table
net/mlx5: Lag, enable hash mode by default for all NICs
net/mlx5: detect and enable bypass port select flow table
Or Gerlitz (1):
net/mlx5e: Rename from tls to transport static params
drivers/infiniband/hw/mlx5/mlx5_ib.h | 12 +
.../ethernet/mellanox/mlx5/core/en/tc/meter.c | 6 +-
.../mlx5/core/en_accel/common_utils.h | 32 ++
.../mellanox/mlx5/core/en_accel/ipsec_rxtx.h | 5 -
.../mellanox/mlx5/core/en_accel/ktls_rx.c | 6 +-
.../mellanox/mlx5/core/en_accel/ktls_tx.c | 8 +-
.../mellanox/mlx5/core/en_accel/ktls_txrx.c | 36 +--
.../mellanox/mlx5/core/en_accel/ktls_utils.h | 17 +-
drivers/net/ethernet/mellanox/mlx5/core/fw.c | 6 +
.../net/ethernet/mellanox/mlx5/core/health.c | 7 -
.../net/ethernet/mellanox/mlx5/core/lag/lag.c | 91 +++++-
.../ethernet/mellanox/mlx5/core/lib/clock.c | 139 +++++++--
.../net/ethernet/mellanox/mlx5/core/main.c | 34 +++
.../mellanox/mlx5/core/steering/dr_types.h | 14 -
.../mellanox/mlx5/core/steering/fs_dr.h | 4 -
include/linux/mlx5/device.h | 70 ++++-
include/linux/mlx5/driver.h | 9 +-
include/linux/mlx5/fs_helpers.h | 48 ---
include/linux/mlx5/mlx5_ifc.h | 280 ++++++++++++++++--
include/linux/mlx5/mlx5_ifc_fpga.h | 24 --
include/linux/mlx5/qp.h | 1 +
21 files changed, 629 insertions(+), 220 deletions(-)
create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/en_accel/common_utils.h
--
2.37.2
