The mlx5 would allocate no less than one irq for per cpu, we can bond each
irq to a cpu to improve interrupt performance.
Signed-off-by: Yajun Deng <yajun.deng@xxxxxxxxx>
---
.../net/ethernet/mellanox/mlx5/core/pci_irq.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
index 662f1d55e30e..d13fc403fe78 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
@@ -624,11 +624,27 @@ int mlx5_irq_table_get_num_comp(struct mlx5_irq_table *table)
return table->pf_pool->xa_num_irqs.max - table->pf_pool->xa_num_irqs.min;
}
+static void mlx5_calc_sets(struct irq_affinity *affd, unsigned int nvecs)
+{
+ int i;
+
+ affd->nr_sets = (nvecs - 1) / num_possible_cpus() + 1;
+
+ for (i = 0; i < affd->nr_sets; i++) {
+ affd->set_size[i] = min(nvecs, num_possible_cpus());
+ nvecs -= num_possible_cpus();
+ }
+}
+
int mlx5_irq_table_create(struct mlx5_core_dev *dev)
{
int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ?
MLX5_CAP_GEN(dev, max_num_eqs) :
1 << MLX5_CAP_GEN(dev, log_max_eq);
+ struct irq_affinity affd = {
+ .pre_vectors = 0,
+ .calc_sets = mlx5_calc_sets,
+ };
int total_vec;
int pf_vec;
int err;
@@ -644,7 +660,8 @@ int mlx5_irq_table_create(struct mlx5_core_dev *dev)
total_vec += MLX5_IRQ_CTRL_SF_MAX +
MLX5_COMP_EQS_PER_SF * mlx5_sf_max_functions(dev);
- total_vec = pci_alloc_irq_vectors(dev->pdev, 1, total_vec, PCI_IRQ_MSIX);
+ total_vec = pci_alloc_irq_vectors_affinity(dev->pdev, 1, total_vec,
+ PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &affd);
if (total_vec < 0)
return total_vec;
pf_vec = min(pf_vec, total_vec);
--
2.25.1
