On 2022/1/7 23:50, Tom Talpey wrote: > Alignment is only part of the issue. The instruction set, type of > mapping, and the width of the bus are also important to determine if > a torn write might occur. > > Off the top of my head, an uncached mapping would be a problem on an > architecture which did not support 64-bit stores. A cache will merge > 32-bit writes, which won't happen if it's disabled. I guess it could > be argued this is uninteresting, in a modern platform, but... > > A second might be MMIO space, or a similar dedicated memory block such > as a GPU. It's completely a platform question whether these can provide > an untorn 64-bit write semantic. Hi Tom, These issues come from differnet arches or devices. Either atomic64_set() or smp_store_release() returns void so how to check these issues in SoftRoCE driver? Sorry, it's not clear for me to add which stricter checks. Best Regards, Xiao Yang
