Add IB_QPT_XRC_INI QP type to rxe_rw_opcode_info.
Signed-off-by: Bob Pearson <rpearsonhpe@xxxxxxxxx>
---
drivers/infiniband/sw/rxe/rxe_opcode.c | 61 +++++++++++++++-----------
1 file changed, 36 insertions(+), 25 deletions(-)
diff --git a/drivers/infiniband/sw/rxe/rxe_opcode.c b/drivers/infiniband/sw/rxe/rxe_opcode.c
index 3ef5a10a6efd..da719abc1846 100644
--- a/drivers/infiniband/sw/rxe/rxe_opcode.c
+++ b/drivers/infiniband/sw/rxe/rxe_opcode.c
@@ -15,53 +15,60 @@ struct rxe_wr_opcode_info rxe_wr_opcode_info[] = {
[IB_WR_RDMA_WRITE] = {
.name = "IB_WR_RDMA_WRITE",
.mask = {
- [IB_QPT_RC] = WR_INLINE_MASK | WR_WRITE_MASK,
- [IB_QPT_UC] = WR_INLINE_MASK | WR_WRITE_MASK,
+ [IB_QPT_RC] = WR_INLINE_MASK | WR_WRITE_MASK,
+ [IB_QPT_UC] = WR_INLINE_MASK | WR_WRITE_MASK,
+ [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_WRITE_MASK,
},
},
[IB_WR_RDMA_WRITE_WITH_IMM] = {
.name = "IB_WR_RDMA_WRITE_WITH_IMM",
.mask = {
- [IB_QPT_RC] = WR_INLINE_MASK | WR_WRITE_MASK,
- [IB_QPT_UC] = WR_INLINE_MASK | WR_WRITE_MASK,
+ [IB_QPT_RC] = WR_INLINE_MASK | WR_WRITE_MASK,
+ [IB_QPT_UC] = WR_INLINE_MASK | WR_WRITE_MASK,
+ [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_WRITE_MASK,
},
},
[IB_WR_SEND] = {
.name = "IB_WR_SEND",
.mask = {
- [IB_QPT_SMI] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_GSI] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_SMI] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_GSI] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_WRITE_MASK,
},
},
[IB_WR_SEND_WITH_IMM] = {
.name = "IB_WR_SEND_WITH_IMM",
.mask = {
- [IB_QPT_SMI] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_GSI] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_SMI] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_GSI] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_WRITE_MASK,
},
},
[IB_WR_RDMA_READ] = {
.name = "IB_WR_RDMA_READ",
.mask = {
- [IB_QPT_RC] = WR_READ_MASK,
+ [IB_QPT_RC] = WR_READ_MASK,
+ [IB_QPT_XRC_INI] = WR_READ_MASK,
},
},
[IB_WR_ATOMIC_CMP_AND_SWP] = {
.name = "IB_WR_ATOMIC_CMP_AND_SWP",
.mask = {
- [IB_QPT_RC] = WR_ATOMIC_MASK,
+ [IB_QPT_RC] = WR_ATOMIC_MASK,
+ [IB_QPT_XRC_INI] = WR_ATOMIC_MASK,
},
},
[IB_WR_ATOMIC_FETCH_AND_ADD] = {
.name = "IB_WR_ATOMIC_FETCH_AND_ADD",
.mask = {
- [IB_QPT_RC] = WR_ATOMIC_MASK,
+ [IB_QPT_RC] = WR_ATOMIC_MASK,
+ [IB_QPT_XRC_INI] = WR_ATOMIC_MASK,
},
},
[IB_WR_LSO] = {
@@ -73,34 +80,38 @@ struct rxe_wr_opcode_info rxe_wr_opcode_info[] = {
[IB_WR_SEND_WITH_INV] = {
.name = "IB_WR_SEND_WITH_INV",
.mask = {
- [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK,
- [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK,
+ [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_WRITE_MASK,
},
},
[IB_WR_RDMA_READ_WITH_INV] = {
.name = "IB_WR_RDMA_READ_WITH_INV",
.mask = {
- [IB_QPT_RC] = WR_READ_MASK,
+ [IB_QPT_RC] = WR_READ_MASK,
+ /* TODO get rid of this no such thing for RoCE */
},
},
[IB_WR_LOCAL_INV] = {
.name = "IB_WR_LOCAL_INV",
.mask = {
- [IB_QPT_RC] = WR_LOCAL_OP_MASK,
+ [IB_QPT_RC] = WR_LOCAL_OP_MASK,
+ [IB_QPT_UC] = WR_LOCAL_OP_MASK,
+ [IB_QPT_XRC_INI] = WR_LOCAL_OP_MASK,
},
},
[IB_WR_REG_MR] = {
.name = "IB_WR_REG_MR",
.mask = {
- [IB_QPT_RC] = WR_LOCAL_OP_MASK,
+ [IB_QPT_RC] = WR_LOCAL_OP_MASK,
+ [IB_QPT_UC] = WR_LOCAL_OP_MASK,
+ [IB_QPT_XRC_INI] = WR_LOCAL_OP_MASK,
},
},
[IB_WR_BIND_MW] = {
.name = "IB_WR_BIND_MW",
.mask = {
- [IB_QPT_RC] = WR_LOCAL_OP_MASK,
- [IB_QPT_UC] = WR_LOCAL_OP_MASK,
+ [IB_QPT_RC] = WR_LOCAL_OP_MASK,
+ [IB_QPT_UC] = WR_LOCAL_OP_MASK,
},
},
};
--
2.30.2
