Re: Power Domain Framework

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Hello,

> This implementation is assuming that the implementation in hardware only
> has two levels, and that the decision to go to the higher level is done
> by a simple or of requests for the full level from the consumers. I'm
> not convinced that this will be true in general, or that it's always
> going to be true that the different power domains are all isolated from
> each other. There doesn't seem to be any immediate reason why hardware
> won't ever implement more than two modes, and I'm not convinced that the
> straight or of requests will always be sufficient to determine the

Yes. Two modes is not the only level that hardware can support.
An ideal case is Full OPP/Half OPP (which is the normal operating
point)/Retention(which is the least so that the device is on).

> operating mode for the entire power domain. For example, I can see
> hardware requiring that if more than a given number of blocks are
> enabled at any level a higher operating point is selected.
Hmm...very much possible. Need to think on this further.

> Are you sure that this interface is sufficiently general to work with
> all hardware, not just your own? How does this map on to the OMAP or SH
> hardware, for example?
AFAIK and with my experience (and my current memory) with TI Davinci
arch, most of the power domains are simpler ones with on/off and
possibly some retention too. And the latest TI code also exposes domains
with on/off/retention states. So, I think if we make this sturdy, I dont
see any reason why we cannot map any generic architecture. CCing Kevin
for his inputs.

This is one of the most important aspect for such a change in the
regulator framework: bringing in the domain aspect can encourage all
newer (possibly older) architectures to come under a generic umbrella.

Anyways, let me have a bit more on the "number of blocks" thing!

Regards,
Sundar


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