Hi, When capturing some traces with dynamic tick we were noticing the interrupt latency seems to go up a good amount. If you look at the trace the gpio IRQ is now offset a good amount. Good news I guess is its pretty predictable. * If we couple this with progressively higher latency C-States we see that IO speed can fall by a good amount, especially for PIO mixes. Now if QOS is maintained you may or may-not care. I was wondering what thoughts of optimizing this might be. One thought was if an io-ondemand of some sort was used. It could track interrupt statistics and be feed back into cpu-idle. When there is a high interrupt load period it could shrink the acceptable latency and thus help choose a good a C-State which favors throughput. Some moving average window could be used to track it. Perhaps a new interrupt attribute could be attached at irq request time to allow the tracking of bandwidth important devices. The attached is captured on a .22 kernel. The same should be available in a bit on a .24 kernel. Regards, Richard W.
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