On Fri, 2006-10-13 at 18:34 +0100, Alan Cox wrote: > Ar Gwe, 2006-10-13 am 10:49 -0600, ysgrifennodd Matthew Wilcox: > > No it didn't. It's undefined behaviour to perform *any* PCI config > > access to the device while it's doing a D-state transition. It may have > > I think you missed the earlier parts of the story - the kernel caches > the base config register state. > > > happened to work with the chips you tried it with, but more likely you > > never hit that window because X simply didn't try to do that. > > Which is why the kernel caches the register state. This all came up long > ago and the solution we currently have was the one chosen after > considerable debate and analysis about things like locking. We preserved > the historical reliable interface going back to the early Linux PCI > support and used by all the apps. Well, we have two different things here. One is short term block. For example, PM transitions, or BIST. In that case, I reckon it might be worth just making the user space PCI config space accessors block in the kernel during the transition (a wait queue ?) One is long term block: the device is off. That's where it becomes tricky. For D3, I suppose it's actually correct to return cached infos provided that those do actually cache the PM capability indicating D3 state (that is we need to update the cache after the transition). And it's correct to prevent writes too I suppose. Then there are problems with things like embedded or some Apple ASICs where we toggle power/clock lines of devices but not directly using PCI PM (in fact, those devices might not even have PCI PM capability exposed). Returning cached info is fine, but we can't tell userland about the powered off (or unclocked) state of the device that way. Ben.
