On Tue, Jul 05, 2005 at 10:46:20PM +0100, Russell King wrote: > On Tue, Jul 05, 2005 at 09:05:55PM +0100, Matthew Wilcox wrote: > > 64-bit BARs work fine on 64-bit machines. I'm ambivalent whether we > > ought to support 64-bit BARs on 32-bit machines. > > This only occurs because the problematical functions (eg, > pci_update_resource) probably aren't called on 64-bit machines - if > they were, they'd zero the upper 32-bits. Maybe 64-bit machines are > happy with that anyway? Why problematical? It's just the way how linux has always dealt with 64-bit BARs - put everything below 4G in the bus address space, on *any* architecture. I'd be quite surprised if some firmware doesn't do the same thing - so far I haven't heard any complaints. Eventually we'll have to support MMIO above 4G, but I suspect this won't be necessary at least in a next couple of years. Anyway, there are no fundamental changes required for the generic PCI layer to handle that, just some tweaks here and there - almost all non-trivial stuff will be arch-specific. > Rather than reimplementing the internals of pci_update_resource() it > may be worth splitting the common stuff out so it gets fixed for both > pci_update_resource() and pci_enable_device(). Just use pci_update_resource(). John, I'd also suggest following changes to the patch: - move the code to pci_set_power_state(), where it belongs to; - explicitly check for D3hot->D0 transition *and* for the No_Soft_Reset bit, to avoid unnecessary config space accesses; - add a quote from PCI spec (as a comment) explaining why is it needed. Ivan.
