On Thursday 17 March 2005 6:32 pm, Benjamin Herrenschmidt wrote: > BTW. David, can't your clock stuff be simply represented in terms of bus & device states as > well ? In most case, it's not PCI, so it could be defined as special bus types with states > matching the various clock states. It's not "my" clock stuff ... I don't design hundreds of chips! ;) Yes and no. I described a canonical situation in IRC, as applied to certain devices. A given device state has consequences in terms of clock usage. Using ACPI terminology, it'd be straightforward to support D0 (operational), D2 (suspend), and D3 (poweroff) states for many peripherals. And folk are using platform_bus for this, nothing special is necessary. Thing is, it's the system power states that are placing clock constraints on devices. On OMAP, going into "deep sleep" means you've got to stop using the 48 MHz clock. For "big sleep", you can keep using that clock. Most other CPUs have similar constraints: multiple system states, defined primarily by clock usage. (Discussing off-chip peripherals like LCDs and backlights adds some orthogonal dimensions. - Dave
