On Wed, Sep 16, 2020 at 03:15:02PM +0100, Lorenzo Pieralisi wrote: > On Wed, Sep 16, 2020 at 09:48:52AM +0100, Catalin Marinas wrote: > > On Wed, Sep 16, 2020 at 09:33:16AM +0100, Will Deacon wrote: > > > On Tue, Sep 15, 2020 at 08:40:06PM -0300, Jason Gunthorpe wrote: > > > > On Wed, Sep 16, 2020 at 09:17:38AM +1000, Benjamin Herrenschmidt wrote: > > > > > With the patch, those device will now use MT_DEVICE_NC. > > > > > > > > Which doesn't do WC at all on some ARM implementations. > > > > > > Is that just TX2? I remember that thing being weird where GRE performed > > > better than NC, but I thought that was a one off (and the thing is dead). > > > > I recall something along these lines. Hopefully ARM updated the guidance > > to licensees. > > > > > NC is more permissive than GRE, so I think that's the right one to use; i.e. > > > we go for the fewest number of restrictions on the hardware. If somebody > > > screws up the uarch, that's up to them. > > > > I agree, Normal NC is better as long as the BAR can tolerate read > > side-effects. > > That we don't know but if a prefetchable BAR can't tolerate read > side effects this would be already a problem on eg x86 - that's > the best we can hope for given the current PCI specs. > > +1 on normal NC. The only open point is whether we should make > arch_can_pci_mmap_wc() return false on platforms like TX2. I lost track in this thread whether it matters. TX2 would need Device GRE for optimal performance but the kernel doesn't currently provide it anyway. We could expose a new memory type, aligned_wc ;). -- Catalin
