Hi Rob, Thanks a lot for your review! > -----Original Message----- > From: Rob Herring <robh@xxxxxxxxxx> > Sent: 2020年9月15日 9:20 > To: Z.q. Hou <zhiqiang.hou@xxxxxxx> > Cc: linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; > linux-kernel@xxxxxxxxxxxxxxx; bhelgaas@xxxxxxxxxx; > shawnguo@xxxxxxxxxx; Leo Li <leoyang.li@xxxxxxx>; > lorenzo.pieralisi@xxxxxxx; gustavo.pimentel@xxxxxxxxxxxx; M.h. Lian > <minghuan.lian@xxxxxxx>; Mingkai Hu <mingkai.hu@xxxxxxx>; Roy Zang > <roy.zang@xxxxxxx> > Subject: Re: [PATCH 2/7] PCI: layerscape: Change to use the DWC common > link-up check function > > On Mon, Sep 07, 2020 at 01:37:56PM +0800, Zhiqiang Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > > > > The current Layerscape PCIe driver directly uses the physical layer > > LTSSM code to check the link-up state, which treats the > L0 states as > > link-up. This is not correct, since there is not explicit map between > > link-up state and LTSSM. So this patch changes to use the DWC common > > link-up check function. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > > --- > > drivers/pci/controller/dwc/pci-layerscape.c | 141 > > ++------------------ > > 1 file changed, 10 insertions(+), 131 deletions(-) > > IIRC, the common function uses a debug register. I've been wondering do > the common PCIe config space registers not work on DWC? If you have an > answer, that would be great for some potential additional cleanups. > You're right it uses a port debug register, but I'm not sure if the Link status Register of common PCIe config space works or not on DWC. Gustavo, can you help answer this query? Regards, Zhiqiang > Either way, > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
