On Thu, 2020-09-03 at 09:08 +1000, Benjamin Herrenschmidt wrote: > On Wed, 2020-09-02 at 18:21 +0100, Catalin Marinas wrote: > > > I understand we do want weak ordering for prefetchable BAR > > > mappings > > > but my worry is that by exposing the resources as WC to user > > > space > > > we are giving user space the impression that those mappings > > > mirror > > > x86 WC mappings behaviour that is not true on ARM64. > > > > Would Device_GRE be close to the x86 WC better? It won't allow > > unaligned > > accesses and that can be problematic for the user. OTOH, it doesn't > > speculate reads, so it's safer from the hardware perspective. > > Its accepted generally that prefetchable BARs can allow speculative > accesses, write combining, re-ordering even etc... and it's also > commonly be the target of unaligned accesses. > > In reality, in PCI land, it really means "no side effects". Correction: No *read* side effects. Cheers, Ben.
