The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The default value is set and it seems pretty certain that enabling link initialization is always required. Maybe it could just be dropped from the Intel driver, but lets move setting it into the common code to be sure. Cc: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> Cc: Jingoo Han <jingoohan1@xxxxxxxxx> Cc: Gustavo Pimentel <gustavo.pimentel@xxxxxxxxxxxx> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> Signed-off-by: Rob Herring <robh@xxxxxxxxxx> --- drivers/pci/controller/dwc/pcie-designware.c | 1 + drivers/pci/controller/dwc/pcie-intel-gw.c | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 448f62f2e6ea..61e1faba15bf 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -553,6 +553,7 @@ void dw_pcie_setup(struct dw_pcie *pci) val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_FAST_LINK_MODE; + val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); ret = of_property_read_u32(np, "num-lanes", &pci->num_lanes); diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c index 2c0d32ffb828..d15e49b8df2a 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -164,10 +164,6 @@ static void intel_pcie_port_logic_setup(struct intel_pcie_port *lpp) val = FIELD_PREP(PORT_AFR_N_FTS_MASK, lpp->n_fts) | FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, lpp->n_fts); pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_AFR, mask, val); - - /* Port Link Control Register */ - pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_LINK_CONTROL, PORT_LINK_DLL_LINK_EN, - PORT_LINK_DLL_LINK_EN); } static void intel_pcie_rc_setup(struct intel_pcie_port *lpp) -- 2.25.1
