> In the future you can use this script to automate some of the tedium > of parsing the eeh dumps: > https://patchwork.ozlabs.org/project/skiboot/patch/20200717044243.1195833-1-oohall@xxxxxxxxx/ Ah, nice, thanks for showing me this! I had written my own parser that just dumped a few register names and what bits were set in each, but your script seems much more feature-complete. > Anyway, for background the way PHB3 and PHB4 handle incoming DMAs goes > as follows: > > 1. Map the 16bit <bus><devfn> number to an IOMMU context, we call > those PEs. PE means "partitionable endpoint", but for the purpose of > processing DMAs you can ignore that and just treat it as an IOMMU > context ID. > 2. Use the PE number and some of the upper bits of the DMA address to > form the index into the Translation Validation Table. > 3. Use the table entry to validate the DMA address is within bounds > and whether it should be translated by the IOMMU or used as-is. > > If the table entry says the DMA needs to be translated by the IOMMU we'll also: > 4. Walk the IOMMU table to get the relevant IOMMU table entry. > 5. Validate the device has permission to read/write to that address. > > The "TVT Address Range Error" you're seeing means that the bounds > checks done in 3) is failing. OPAL configures the PHB so there's two > TVT entries (TVEs for short) assigned to each PE. Bit 59 of the DMA > address is used to select which TVE to use. We typically configure > TVE#0 to map 0x0...0x8000_0000 so there's a 2GB 32bit DMA window. > TVE#1 is configured for no-translate (bypass) mode so you can convert > from a system physical address to a DMA address by ORing in bit 59. Thanks for the in-depth explanation, I find these low-level details really fascinating. > From word 2 of the PEST entry the faulting DMA address is: > 0x0000203974c00000. That address is interesting since it looks a lot > like a memory address on the 2nd chip, but it doesn't have bit 59 set > so TVE#0 is used to validate it. Obviously that address is above 2GB > so we get the error. Ah, I see. Do you know if the information on the PEST registers is documented publicly somewhere? I tried searching for what those registers meant in the PHB4 spec but it basically just said, "the PEST registers contain PEST data," which isn't particularly helpful. > What's probably happening is that the ASmedia controller doesn't > actually implement all 64 address bits and truncates the upper bits of > the DMA address. Doing that is a blatant violation of the PCIe (and > probably the xHCI) spec, but it's also pretty common since "it works > on x86." Something to try would be booting with the iommu=nobypass in > the kernel command line. That'll disable TVE#1 and force all DMAs to > go through TVE#0. Thanks, iommu=nobypass fixed it! Plugging in one or more USB devices no longer triggers any EEH errors. > Assuming the nobypass trick above works, what you really need to do is > have the driver report that it can't address all 64bits by setting its > DMA mask accordingly. For the xhci driver it looks like this is done > in xhci_gen_setup(), there might be a quirks-style interface for > working around bugs in specific controllers that you can use. Have a > poke around and see what you can find :) Yup, the xhci driver has a quirks system, and conveniently one of those is XHCI_NO_64BIT_SUPPORT. After making a 3-line patch to xhci-pci.c to add that quirk for this chip, the host controller is now able to work without setting iommu=nobypass in the kernel arguments. Thank you so much for your help! You've likely saved me several hours of reading documentation, as well as several more hours of fiddling around with the xhci driver. I'm almost disappointed the fix was so simple, but the time savings alone more than makes up for it. I'll submit the patch to the USB ML shortly. Thanks again! Forest
