On Monday 13 July 2020 17:41:40 Lorenzo Pieralisi wrote: > On Mon, Jul 13, 2020 at 04:50:03PM +0200, Pali Rohár wrote: > > On Monday 13 July 2020 12:23:25 Lorenzo Pieralisi wrote: > > > I will go over the thread again but I suspect I can merge the patch even > > > though I still believe there is work to be done to understand the issue > > > we are facing. > > > > Just to note that pci-mvebu.c also checks if pcie link is up before > > trying to access the real PCIe interface registers, similarly as in my > > patch. > > I understand - that does not change my opinion though, the link check > is just a workaround, it'd be best if we pinpoint the real issue which > is likely to a HW one. Lorenzo, if you have an idea how to debug this issue or if you would like to see some test results, let me know. I can do some tests, but I currently really do not know more then what I wrote in previous emails. In my opinion, problem is in HW which Marvell has not documented nor proved that it exists. Other option is that problem is in Compex card which can be triggered only by Marvell aardvark HW.
